ISIS Neutron and Muon Source Data Journal

Evaluation of a fault-tolerant RISC-V

Abstract: The RISC-V architecture is an initiative of academia and industry for embedded systems solutions. This architecture consists of a set of instructions developed to be open and free, facilitating and optimizing the implementations. Although its specification is open, the solutions currently available do not meet the requirements of some applications, such as space applications. Thus, our research team developed a RISC-V soft-core processor focusing on the implementation of fault tolerance techniques for use in embedded computer systems in critical environments. We intend to use the ChipIr facility to produce a realistic evaluation of the reliability of the developed RISC-V processor in an actual radioactive environment. The outcome of this study will allow us to evince the behavior of the processor core in a real critical environment.

Principal Investigator: Dr Luigi Dilillo
Experimenter: Mr Thierry Gil
Experimenter: Mr Lucas Matana Luza
Experimenter: Mr Daniel Söderström
Local Contact: Dr Carlo Cazzaniga

DOI: 10.5286/ISIS.E.RB2010053

ISIS Experiment Number: RB2010053

Publisher: STFC ISIS Neutron and Muon Source

Data format: RAW/Nexus
Select the data format above to find out more about it.

Data Citation

The recommended format for citing this dataset in a research publication is as:
[author], [date], [title], [publisher], [doi]

For Example:
Dr Luigi Dilillo et al; (2020): Evaluation of a fault-tolerant RISC-V, STFC ISIS Neutron and Muon Source, https://doi.org/10.5286/ISIS.E.RB2010053

Data is released under the CC-BY-4.0 license.