ISIS Neutron and Muon Source Data Journal

Validation of Partial Duplication With Compare for FPGA Systems

Abstract: Duplication with compare (DWC) is a digital logic design technique that is used to detect errorscaused by single-event upsets. This technique duplicates the system logic and insertscomparators to identify run-time logic faults. It is especially useful in Field Programmable GateArrays used in high availability systems to immediately detect FPGA CRAM upsets. We havedeveloped a design tool that automatically applies partial duplication on FPGA designs. Thisproposed work will test the viability of partial DWC on a complex FPGA networking design. Byapplying a neutron beam to the FPGA we can evaluate the effects of the FPGA design withoutusing the partial DWC technique and then evaluate the benefits of using partial DWC on the sameFPGA design. We anticipate that we will be able significantly reduce the presence of silent controlcorruption errors caused by FPGA CRAM upsets.

Principal Investigator: Dr Michael Wirthlin
Experimenter: Mr Andrew Keller
Experimenter: Mr Jared Anderson
Local Contact: Dr Carlo Cazzaniga

DOI: 10.5286/ISIS.E.RB1900120

ISIS Experiment Number: RB1900120

Publisher: STFC ISIS Neutron and Muon Source

Data format: RAW/Nexus
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Data Citation

The recommended format for citing this dataset in a research publication is as:
[author], [date], [title], [publisher], [doi]

For Example:
Dr Michael Wirthlin et al; (2019): Validation of Partial Duplication With Compare for FPGA Systems, STFC ISIS Neutron and Muon Source, https://doi.org/10.5286/ISIS.E.RB1900120

Data is released under the CC-BY-4.0 license.